(1) Field of the Invention
The present invention relates, in general, to the integrity and reliability of semiconductor chip interconnections and, more specifically, to the methods of fabricating multi-layer wiring structures on semiconductor chips for relieving thermal stresses on solder ball interconnections.
(2) Description of the Prior Art
The advent of VLSI technology in the semiconductor field has resulted in the demand for high density packaging. Semiconductor packaging traditionally has three levels of package. In the first level, a single chip module comprises a semiconductor chip attached to a substrate that includes interconnections to the next level of package. The substrate and chip assembly is usually molded in an encapsulant for environmental protection. In the second level of packaging, a printed circuit card typically mounts to the single chip modules. Finally, the third level package is usually a planar printed circuit board.
The utilization of VLSI semiconductor chips in commercial electronic products such as cameras, camcorders, DVD players, etc., requires that semiconductor packages be highly reliable and space efficient in their designs. In addition, military applications require lightweight, space efficient, highly reliable packaging structures. Elimination of a level of packaging has been a driving force in electronic system design in the recent past. This reduction would allow for closer spacing of semiconductor chips and also reduce signal delays. In addition, the reduction of a level of packaging would increase product reliability and decrease product costs. One design currently in use is direct chip attach. In this design, integrated circuits are flip chip mounted onto a substrate, usually ceramic, and then the assembly is sealed in an enclosure for environmental protection. The environmental protection is required to protect the semiconductor and the interconnections against corrosive elements and mechanical disturbances. Unfortunately, the inclusion of enclosures for environmental protection results in larger packages with longer distances between semiconductor chips. This also creates longer signal delays.
In addition, advances in VLSI technology in the semiconductor field have created the need for higher interconnection density on the surface of the semiconductor chip. Such interconnections are used to connect between chip terminals and the next level of packaging or to a printed circuit board. The requirement for higher density interconnections is created by the advent of smaller circuit devices fabricated in recent manufacturing processes. These smaller circuits, in turn, result in higher circuit counts per chip. These higher circuit counts further require the addition of signal input and output connections. In addition, the higher circuit counts increase the power requirements and connectivity of the chips. This need for higher interconnection density has resulted in interconnection techniques such as the use of solder bumps. Solder bump interconnect systems utilize the total area overlying the chip and thus providing more interconnections per chip.
One significant challenge that must be overcome when using solder bumps is the issue of thermally induced mechanical stress. These mechanical stresses in the solder bump result from differences in the thermal coefficient of expansion (TCE) of the basic materials used, such as between the silicon substrate, the metal interconnects, and the solder bumps. In an application where the product utilizes a silicon semiconductor chip and the next level of package is an epoxy—glass printed circuit card and the product usage is in a home or office environment—the resultant thermally induced strains are such that the solder of the solder bumps is stressed beyond the elastic limit of the material. Solder fatigue cracks develop due to the ON-OFF thermal cycling that occurs during normal product usage. These fatigue cracks eventually result in faulty interconnections and, therefore, represent a serious reliability concern.
In order to minimize the thermal stresses on the solder ball interconnections a method currently in use is shown, in cross section, in FIG. 1. The semiconductor chip 10 has an interconnecting wiring structure 12 fabricated by conventional photolithography. The wiring structure 12 is composed of copper Cu or aluminum Al metallurgy with polyimide for the insulator. Polyimide is known to have a low coefficient of thermal expansion. A buffer layer 14 is added to the above structure by soldering or by pressure metal bonding the interconnections. Solder balls 16 are added by plating or evaporation. The buffer layer 14 comprises a low modulus elastomer with thru metal vias for interconnections. The buffer layer 14 provides stress relief that is required when the chip scale package is interconnected to the next level package. If this method is used to directly mounted chip scale packaging onto printed circuit boards, then additional processes are required to add the buffer layer. In addition, electrical delay is increased in the final circuit.
A drawback to the chip scale packaging design is that the basic materials used, silicon for the semiconductor chip, and glass-epoxy for the printed circuit cards and boards, have different thermal coefficients of expansion TCE. The TCE for silicon based materials ranges from 2.5-3.5 ppm/0 C whereas the TCE for glass-epoxy structures is in the range of 15-25 ppm/0 C. This difference in TCE results in thermally induced stresses in the solder ball interconnections when the product is in use. The stresses in the solder ball interconnections are due to the thermally induced strains when the product is thermally cycled during use.
Several prior art inventions relate to the design of semiconductor devices with thermal stress relief. U.S. Pat. No. 6,028,364 to Ogino et al describes a design utilizing an elastomer for thermal stress relief on a bumped semiconductor chip. U.S. Pat. No. 6,395,581 to Choi describes a method for fabricating a BGA semiconductor package utilizing a metal powder as a flexible member for improved solder joint reliability. U.S. Pat. No. 6,423,571 to Ogino et al provides a method for making semiconductor solder bumped chip structures utilizing an elastomer for the dielectric material as a stress relieving mechanism.